The present invention relates to a dynamic random access memory (DRAM) device having a plurality of one-transistor type memory cells, and more particularly to a DRAM device having trench capacitors in respective memory cells.
A memory cell composed of a single MOS transistor and a single capacitor has been widely used to realize a high integration of the memory device. Further, to reduce an area of the capacitor, a method has been proposed in which a trench is dug in a silicon substrate and a capacitor, that is called a trench capacitor, is formed by making use of an side wall surface and a bottom wall surface of this trench. The memory cell can realize a high integration since the side wall of the groove is utilized as the capacitor section. However, depletion layers extending from the trenches of respective memory cells in their operation would cause a punch-through phenomenon between trenches. Therefore, the interval between trenches cannot be shorter, and further high integration is restrained. As a countermeasure of the problem, two kinds of memory devices have been proposed in EUROPEAN PATENT APPLICATION Publication number 0 108 390. As one memory device, a high impurity region (P.sup.+ -type region) of the same conductivity type as that of a semiconductor substrate (P-type substrate) is provided outside the trench so that the P.sup.+ -type impurity region forms the entire wall of the trench from the bottom to the major surface of the substrate, and a source or drain region of the transfer gate transistor is connected to a conductive material (capacitor electrode) filled within the trench via a dielectric film. This construction can prevent the unfavorable punch-through phenomenon between trenches. However, in the operation, a minute depletion layer is inevitably produced between the dielectric film and the trench wall, that is, the P.sup.+ -type region, and therefore the capacitance per unit wall area is decreased. In the other kind of devices, the P.sup.+ -type region mentioned above is replaced by an N.sup.+ -type region. The changed construction can also prevent the punch-through phenomenon between trenches. Further, any depletion layer is not produced between the trench wall, that is, the N.sup.+ -type region and the dielectric film, and therefore the reduction of the capacitance does not occur. However, the N.sup.+ -type regions in respective memory cells should not be a floating state, that is, they must be connect to a fixed potential line such as a ground potential. Therefore, in the prior art, the substrate consists of an N-type silicon body and a P-type epitaxial silicon layer formed on the N-type silicon body. The transfer gate transistors are provided on the P-type epitaxial silicon layer, and the trench capacitors are provided such that trenches are formed from the front major surface of the P-type epitaxial silicon layer, that is, the front major surface of the substrate per se to the N-type silicon body through the P-type epitaxial silicon layer, and that the N.sup.+ -type regions are formed at the entire wall of the respective trenches from the major surface of the epitaxial silicon layer into the N-type silicon body. Therefore, to the respective N.sup.+ -type regions of the capacitors a fixed potential such as ground potential can be applied through the N-type silicon body. However, in the prior art, a back-gate-bias voltage of, for example, minus (-) 3 volt, which controls the threshold voltage of the transistors (N-channel type transistors), cannot be supplied to the back major surface of the substrate because of existing entirely the N-type silicon body. On the other hand, when the back-gate-bias voltage is applied from some contact portions of the front major surface of the P-type epitaxial silicon layer, an adequate and uniform voltage cannot be supplied to all of the transfer gate transistors in the memory device, because the P-type epitaxial silicon layer in which the transfer gate transistors are provided has a low impurity concentration, that is, a high specific resistivity of, for example, 10 to 20 .OMEGA.-cm. If the number of the contact portions on the front major surface would be increased to that of the memory cells to reduce the electric resistance between each contact portion and the corresponding transistor and to supply an adequate and uniform back-gate-bias voltage to respective transfer transistors in the memory device, the integration would decrease to the extent of unpractical degree. Further, in the prior art structure, the isolation between the N.sup.+ -type source or drain region of the transfer gate transistor and the N.sup.+ -type region of the trench capacitor depends on only an insulating layer on the front major surface because both of the N.sup.+ -type source or drain region of the transistor and the N.sup.+ -type region of the capacitor are formed on and from the front major surface. Therefore, a higher integration cannot be expected because a necessary isolation-distance depends only on the front major surface of the substrate.